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SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
Name
int
reset
Value
0
1
0
1
Description
No interrupt will be sent.
Send interrupt to processor by pulling the INT pin down and setting corresponding status
register bit high to notify that program has ended. Interrupt can only be cleared by reading
interrupt status register 0CH.
Keep the current PWM value.
Set PWM value to 0.
X means do not care whether 1 or 0.
TRIGGER
Wait or send triggers can be used to e.g. synchronize operation between different channels. Send trigger
command takes sixteen 32 kHz clock cycles and wait for trigger takes at least sixteen 32 kHz clock cycles. The
receiving channel stores sent triggers. Received triggers are cleared by wait for trigger command if received
triggers match to channels defined in the command. Channel waits for until all defined triggers have been
received.
External trigger input signal must be at least two 32 kHz clock cycles (= 61 μ s typ.) long to be recognized.
Trigger output signal is three 32 kHz clock cycles (92 μ s typ.) long. External trigger signal is active low, i.e. when
trigger is sent/received the pin is pulled to GND. Sent external trigger is masked, i.e. the device which has sent
the trigger will not recognize it. If send and wait external trigger are used on the same command, the send
external trigger is executed first, then the wait external trigger.
Table 15. Trigger command
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
EXT
wait trigger <5:0>
X B
G
R
EXT
send trigger <5:0>
X B
G
R
X
Name
wait trigger<5:0>
send trigger<5:0>
Value(d)
0-31
0-31
Description
Wait for trigger for the channel(s) defined. Several triggers can be defined in the same
command. Bit 0 is R, bit 1 is G, bit 2 is B and bit 5 is external trigger I/O. Bits 3 and 4
are not in use.
Send trigger for the channel(s) defined. Several triggers can be defined in the same
command. Bit 0 is R, bit 1 is G, bit 2 is B and bit 5 is external trigger I/O. Bits 3 and 4
are not in use.
X means do not care whether 1 or 0.
POWER SAVE MODE
Automatic power save mode is enabled when PWRSAVE_EN bit in register address 08H is 1. Almost all analog
blocks are powered down in power save, if external clock is used. Only charge pump protection circuits remain
active. However if internal clock has been selected only charge pump and led drivers are disabled during power
save since digital part of the LED controller need to remain active. In both cases charge pump enters 'weak 1x'
mode. In this mode charge pump utilizes a passive current limited keep-alive switch, which keeps the output
voltage at battery level.
During program execution LP5521 can enter power save if there is no PWM activity in R, G and B outputs. To
prevent short power save sequences during program execution, LP5521 has command look-ahead filter. In every
instruction cycle R, G, B commands are analyzed, and if there is sufficient time left with no PWM activity, device
will enter power save. In power save program execution continues uninterruptedly. When a command that
requires PWM activity is executed, fast internal startup sequence will be started automatically. Following tables
describe commands and conditions that can activate power save. All channels (R,G,B) need to meet power save
condition in order to enable power save.
20
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